Generally, a semiconductor memory device has a row address counter capable of supporting auto bank refresh operation and a self refresh operation.
FIG. 1 is a circuit diagram illustrating a conventional address counter, FIG. 2 is a circuit diagram illustrating a clock generator in FIG. 1, FIG. 3 is a circuit diagram illustrating a T-flip flop in FIG. 1, and FIG. 4 is a timing chart illustrating the detailed operation of the address counter circuit in FIG. 1.
The address counter in FIG. 1 which is an N-bit address counter has a clock generator and N numbers of negative edge triggered T-flip flops
Hereinafter, the detailed operation of the conventional address counter will be illustrated referring to the accompanying drawings.
When a self refresh request signal SREFREQP, which is internally generated within a DRAM, or an auto-refresh command from an external circuit is toggled to a high level, a clock signal REF_CLK is outputted with a constant delay width by the clock generator of FIG. 2.
This clock signal REF_CLK is inputted into a row address counter and N numbers of row address signals are then outputted therefrom.
As shown in FIG. 4, whenever the clock signal REF_CLK is toggled, the row address signals are sequentially increased.
However, this conventional address counter makes it difficult to implement a per-bank refresh. In the per-bank refresh operation, the refresh operation is carried out for only one bank instead of all the banks and typical read or write operations are carried out in other banks while such a specific bank is refreshed by the per-bank refresh command.
In order to implement the per-bank refresh only upon the specific bank, the bank address should be sequentially and internally counted based on a round-robin manner.
However, since the conventional address counter circuit has no a bank address counter and does not have a configuration capable of controlling the address count based on whether the refresh is in the per-bank refresh mode, the all-bank refresh mode or the self refresh mode, the per-bank refresh is not supported in the conventional address counter circuit.